Waveform track-and-hold circuit

ABSTRACT

A waveform track-and-hold circuit receives an analog input signal and generates an analog output signal. The waveform track-and-hold circuit includes a differential separating input stage, a differential separating output stage, first and second charge storage means, and switch means. The first and second charge storage means are coupled between the differential separating input stage and the differential separating output stage, and the switch means are controlled by a logic control signal so as to selectively isolate the first and second charge storage means from the analog input signal. Additionally, the differential separating input stage includes a push-pull input stage connected to the switch means and receiving the analog input signal. In a preferred embodiment, the analog input signal is supplied to the emitters of transistors that form the push-pull input stage, the collectors of the transistors are connected to the switch means, and the transistors are part of current mirror circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority from prior ItalianPatent Application No. TO-98-A000416, filed May 15, 1998, the entiredisclosure of which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic circuits, and morespecifically to a waveform track-and-hold circuit that receives ananalog input signal and generates an analog output signal under controlof a logic control signal that identifies track operating phases andhold operating phases.

2. Description of Related Art

Waveform track-and-hold circuits, which are also known as“sample-and-hold” circuits, are most often used in association withanalog-to-digital converters. Such circuits perform a sampling operationon continuous waveforms and then store the fetched value. In otherwords, waveform track-and-hold circuits perform input voltage trackingoperations and store the corresponding value at the time instant when acontrol signal is applied. In general, waveform track-and-hold circuitshave an analog input for the waveform to be sampled, an analog output,and a logic control input that receives a control signal (e.g., from amultiplexer). When the control signal is in a predetermined logic state(e.g., a high logic state), the waveform track-and-hold circuit behaveslike a unitary gain linear amplifier or, if required, with apredetermined gain (i.e., the output waveform is a reproduction of thewaveform at the analog input). The transition of the control signal fromthe high logic level to a low logic level enables a “hold” or storagephase.

FIG. 1 shows a conventional waveform track-and-hold circuit. Thewaveform track-and-hold circuit 1 includes an input buffer IB thatreceives the input voltage VIN (i.e., the signal to be sampled). Theinput buffer IB and an output buffer OB of the circuit are usuallyformed by emitter follower amplifiers. The output of the input buffer IBis supplied to a switch S, which is usually formed by a MOSFETtransistor and controlled by a logic control signal VCK. A storagecapacitor CH is then provided and followed by the output buffer OB,which supplies an output voltage VOUT (i.e., the waveform produced bythe waveform track-and-hold circuit 1).

FIG. 1 also shows, in the form of an equivalent circuit, some undesiredeffects that are present in the conventional waveform track-and-holdcircuit 1. A capacitance CS placed between the input of the logiccontrol signal VCK and the input of the output buffer OB represents the“charge dump” effect that causes a raising of the voltage level storedduring transition from the high logic signal to the low logic signal(i.e., a switch-over from the track phase to the hold phase).

A current generator IDR models the “droop rate” phenomenon, which is areduction of the voltage value stored in the storage capacitor CH duringthe hold phase due to the small input current of the output buffer OBthat slowly discharges the storage capacitor. A capacitor CFT representsthe “feed-through” phenomenon, which is a charge injection during thehold phase that is due to the presence of parasitic capacitances in thetransistor acting as the switch S. This also modifies the voltage valuestored in the storage capacitor CH and directly reflects on the accuracyof a converter associated with the waveform track-and-hold circuit.

In order to overcome these drawbacks, it is known to employ differentialstructures such as those used in the waveform track-and-hold circuit 2of FIG. 2. (In the following description, a differential circuit isdefined as a circuit whose output signal depends on the difference ofthe input signals through a transfer function, such as an amplificationratio.) The waveform track-and-hold circuit 2 of FIG. 2 includes adifferential input buffer DIB that receives both a positive input signalINP and a negative input signal INN. Two switches SP and SN receive theoutput signals OUTP′ and OUTN′ of the differential input buffer DIB andare followed by a first storage capacitor CI and a second storagecapacitor C2, respectively. A differential output buffer DOB is provideddownstream and produces two differential output signals OUTP and OUTN.

The “charge dump” effect is removed from the waveform track-and-holdcircuit 2 of FIG. 2 because both switches SP and SN introduce the samecharge amount (i.e., it is suppressed using differential outputsignals). Similarly, at least under a first approximation, the “drooprate” is equal for both differential output signals OUTP and OUTN, andso it is compensated. However, the “feed-through” issue remains, but itcan be solved by connecting some capacitors between the collector of thetransistor forming the differential stage of the differential inputbuffer DIB and the capacitor on the opposite output of the differentialinput stage DIB.

For example, in FIG. 2, the capacitor for the waveform track-and-holdcircuit 2 is connected between the collector of the transistor whosebase receives the output signal OUTP and the second storage capacitorC2. For further details, reference is made to an article by P. Vorenkampand J. P. M. Verdaasdonk entitled “Fully Bipolar, 120-Msample/s 10-bTrack-and-Hold Circuit” (IEEE Journal of Solid State Circuitry, vol. 27,No. 7, Jul. 1992), which is herein incorporated by reference.

However, conventional differential circuits of the type described abovestill have drawbacks. For example, they are not very flexible withrespect to the type of control signal that can be sent, so it isdifficult to drive the switches with CMOS signals without employing aCMOS-to-ECL signal converter. This may be a particular nuisance forhybrid circuits. Furthermore, additional capacitors are required tolower the feed-through during the hold phase. Additionally, thedifferential input stage is particularly sensitive to thermal drifts ofthe input transistors. This can lead to acquisition errors that areespecially harmful if the waveform track-and-hold circuit is used for ananalog-digital converter.

SUMMARY OF THE INVENTION

In view of these drawbacks, it is an object of the present invention toovercome the above-mentioned drawbacks and to provide a waveformrack-and-hold circuit that has a more efficient and improvedperformance.

It is another object of the present invention to provide a waveformtrack-and-hold circuit that has reduced feed-through during the holdphase.

Still another object of the present invention is to provide a waveformtrack-and-hold circuit that compensates for transistor thermal drifts.

A further object of the present invention is to provide a waveformtrack-and-hold circuit that with low complexity and a consequent highoperating frequency.

Yet another object of the present invention is to provide a waveformtrack-and-hold circuit that can use an ECL logic control signal.

One embodiment of the present invention provides a waveformtrack-and-hold circuit that receives an analog input signal andgenerates an analog output signal. The waveform track-and-hold circuitincludes a differential separating input stage, a differentialseparating output stage, first and second charge storage means, andswitch means. The first and second charge storage means are coupledbetween the differential separating input stage and the differentialseparating output stage, and the switch means are controlled by a logiccontrol signal so as to selectively isolate the first and second chargestorage means from the analog input signal. Additionally, thedifferential separating input stage includes a push-pull input stageconnected to the switch means and receiving the analog input signal. Ina preferred embodiment, the analog input signal is supplied to theemitters of transistors that form the push-pull input stage, thecollectors of the transistors are connected to the switch means, and thetransistors are part of current mirror circuits.

Other objects, features, and advantages of the present invention willbecome apparent from the following detailed description. It should beunderstood, however, that the detailed description and specificexamples, while indicating preferred embodiments of the presentinvention, are given by way of illustration only and variousmodifications may naturally be performed without deviating from thepresent invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a first conventional waveformtrack-and-hold circuit;

FIG. 2 shows a block diagram of a second conventional waveformtrack-and-hold circuit;

FIG. 3 shows a schematic diagram of a waveform track-and-hold circuitaccording to a preferred embodiment of the present invention;

FIG. 4a shows a diagram of waveforms generated by the waveformtrack-and-hold circuit of FIG. 3; and

FIG. 4b shows a diagram of control signals employed by the waveformtrack-and-hold circuit of FIG. 3.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described indetail hereinbelow with reference to the attached drawings.

FIG. 3 shows a waveform track-and-hold circuit 3 according to apreferred embodiment of the present invention. The waveformtrack-and-hold circuit 3 has a quasi-differential architecture, which inthe illustrative embodiment of FIG. 3 is formed with bipolartransistors. (A circuit with a quasi-differential architecture isdefined as a circuit that performs a differential transfer function inthe input-output ratio, but without a coupling between differentialbranches defining a common mode node.)

The waveform track-and-hold circuit 3 provides the positive analog inputsignal INP reaching an input buffer circuit IBP. The input buffercircuit IBP has its own storage node NP that is connected to a firststorage capacitor C1. An output buffer circuit OBP is then connected tothe storage node NP and supplies a positive analog output signal OUTP.Because of the quasi-differential architecture, a push-pull structure isprovided in which a negative analog input signal INN reaches an inputbuffer circuit IBN. The input buffer circuit IBN has its own storagenode NN that is connected to it second storage capacitor C2. An outputbuffer circuit OBN is then connected to the storage node NN and itsupplies a negative analog output signal OUTN.

A logic control signal VCK is received at the input of a first pair ofswitches SP1 and SP2, which control both input buffer circuit INP andinput buffer circuit INN. Similarly, a complementary logic controlsignal VCKN is received at the input of a second pair of switches SN1and SN2 for specular control of both input buffer circuit INP and inputbuffer circuit INN. The input buffer circuit IBP is formed by a class ABamplifier that consists of bipolar transistors Q3, Q10, Q2, and Q9 andcurrent generators 15 and 12. The input buffer circuit IBP isessentially two current mirrors (one formed by transistors Q3 and Q2 andthe other formed by transistors Q10 and Q9) that appear to be connectedin a push-pull configuration. Transistors Q3 and Q10 operate asinjection transistors in the current mirror (i.e., they receive currentsimposed by current generators 15 and 12), and transistors Q3 and Q2 havetheir collectors short-circuited with their bases. The input signal INPis injected on the emitter of transistors Q3 and Q10.

In the track phase, the logic control signal VCK is at the low logiclevel so the complementary logic control signal VCKN is at the highlogic level. In such a case, both the first pair of switches SP1 and SP2and the second pair of switches SN1 and SN2 are open circuits that allowthe input buffers IBN and IBP to operate according to their usualoperating mode. As a result, both the positive output signal OUTP andthe negative output signal OUTN track their respective input signals INPand M.

When the logic control signal VCK reaches the high logic level to causea hold phase, transistors Q7 and Q13 (which form the first pair ofswitches SP1 and SP2) are brought to a diode configuration, so thecurrent supplied by current generators I1 and I5 flows through theminstead of flowing through transistors Q3 and Q10. Thus, transistors Q3and Q10 are at cutoff (because the common mode of the input signal INPis at about half the supply voltage). Consequently, transistors Q2 andQ9 complementing the input buffer circuit IBP are also at cutoff.Therefore, the value of the positive input signal at the samplinginstant is stored in the first storage capacitor C1 (i.e., when thelogic control signal VCK reaches the high logic level).

During the hold phase, the positive analog input signal INP has less ofan opportunity to cause a feed-through phenomenon through the parasiticcapacitances of either transistor Q10 or transistor Q3. Consideringtransistor Q3 by way of example, during the hold phase the positiveanalog input signal INP finds a low impedance path as it is injectedthrough the base-emitter capacitance of transistor Q3, which has inparallel the emitter of transistor Q13 of switch SN1. Therefore, thechanges of the positive analog input signal INP cannot appreciablychange the value stored in the first storage capacitor C1.

FIG. 4a shows the trend of the positive analog input signal INP and therepresentative curve of the analog output signal OUTP in line with thelogic control signal VCK shown in FIG. 4b. The analog input signal INPis a sinusoidal signal with a 50 MHZ frequency that is sampled by alogic control signal VCK at a 100 Hz frequency. The logic control signalVCK is an ECL (Emitter Coupled Logic) logic signal, so the high logiclevel controlling the hold phase is equivalent to +1 volts and the lowlogic level controlling the track phase is equivalent to −1 volts. Onthe other hand, CMOS signals can be applied to the switches to obtain anequally efficient operation, even if transistors Q7, Q8, Q13, and Q14are bipolar transistors.

Advantageously, the waveform track-and-hold circuit of the presentinvention has a low feed-through during its hold phase. In particular,during this phase, a low impedance path through the switches is obtainedto hinder the input signal from changing the value stored in thecapacitor. Further, the high degree of symmetry in the circuitryprovides an excellent compensation for the effects caused by temperaturechanges. Additionally, the waveform track-and-hold circuit of thepresent invention can advantageously employ both ECL logic signals andlogic signals pertaining to the MOS family as control signals for theswitches, without having to provide any converters between logicfamilies. The waveform track-and-hold circuit of the present inventionalso has a low complexity that allows a high operating frequency.

While the embodiments of the present invention described above areformed using bipolar transistors, the simple circuitry allows thewaveform track-and-hold circuit of the present invention to also beeasily obtained by one of ordinary skill in the art using CMOStechnology. For example, a CMOS embodiment of the present invention canbe obtained by simply replacing the NPN transistors with N-channel MOStransistors and the PNP transistors with P-channel MOS transistors inthe disclosed embodiments.

While there has been illustrated and described what are presentlyconsidered to be the preferred embodiments of the present invention, itwill be understood by those skilled in the art that various othermodifications may be made, and equivalents may be substituted, withoutdeparting from the true scope of the present invention. Additionally,many modifications may be made to adapt a particular situation to theteachings of the present invention without departing from the centralinventive concept described herein. Furthermore, an embodiment of thepresent invention may not include all of the features described above.Therefore, it is intended that the present invention not be limited tothe particular embodiments disclosed, but that the invention include allembodiments falling within the scope of the appended claims.

What is claimed is:
 1. A waveform track-and-hold circuit that receivesan analog input signal and generates an analog output signal, thewaveform track-and-hold circuit having a track operating phase and ahold operating phase, said waveform track-and-hold circuit comprising: adifferential separating input stage; a differential separating outputstage; first and second charge storage means coupled between thedifferential separating input stage and the differential separatingoutput stage; and switch means controlled by a logic control signal soas to selectively isolate the first and second charge storage means fromthe analog input signal, wherein the differential separating input stageincludes a push-pull stage at the input of differential separating inputstage that the push-pull stage receives the analog input signal, thepush-pull stage being connected to the switch means.
 2. The waveformtrack-and-hold circuit as defined in claim 1, wherein the analog inputsignal is supplied to the emitters of transistors that form thepush-pull input stage, and the collectors of the transistors areconnected to the switch means.
 3. The waveform track-and-hold circuit asdefined in claim 2, wherein the switch means form ECL logic gatesconfigurations.
 4. The waveform track-and-hold circuit as defined inclaim 2, wherein the transistors that form the push-pull input stage arepart of current mirror circuits.
 5. The waveform track-and-hold circuitas defined in claim 1, wherein a negated control signal is generatedfrom the control signal.
 6. The waveform track-and-hold circuit asdefined in claim 1, wherein the control signal controls transistors fora ground portion of the input stage, and the negated control signalcontrols transistors for a supply voltage portion of the input stage. 7.The waveform track-and-hold circuit as defined in claim 1, wherein theswitch means provides a low impedance path during the hold operatingphase.
 8. The waveform track-and-hold circuit as defined in claim 1,wherein the switch means is located upstream of the first and secondcharge storage means.
 9. A waveform track-and hold circuit that receivesan analog input signal and generates an analog output signal, thewaveform track-and-hold circuit having a track operating phase and ahold operating phase, said waveform track-and-hold circuit comprising: adifferential separating input stage; a differential separating outputstage; first and second charge storage means coupled between thedifferential separating input stage and the differential separatingoutput stage; and switch means controlled by a logic control signal soas to selectively isolate the first and second charge storage means fromthe analog input signal, wherein the differential separating input stageincludes a push-pull stage the receives the analog input signal, thepush-pull input stage being connected to the switch means, and thedifferential separating input stage has a quasi-differentialarchitecture.
 10. A waveform track-and-hold circuit that receives ananalog input signal and generates an analog output signal, the waveformtrack-and-hold circuit having a track operating phase and a holdoperating phase, said waveform track-and-hold circuit comprising: adifferential separating input stage; a differential separating outputstage; first and second charge storage means coupled between thedifferential separating input stage and the differential separatingoutput stage; and switch means controlled by a logic control signal soas to selectively isolate the first and second charge storage means fromthe analog input signal, wherein the differential separating input stageincludes a push-pull input stage the receives the analog input signal,the push-pull input stage being connected to the switch means, and theswitch means form ECL logic gates configurations.
 11. An informationhandling system including at least one waveform track-and-hold circuitthat receives an analog input signal and generates an analog outputsignal, the waveform track-and-hold circuit having a track operatingphase and a hold operating phase, said waveform track-and-hold circuitcomprising: a differential separating input stage; a differentialseparating output stage; first and second storage elements coupledbetween the differential separating input stage and the differentialseparating output stage; and a plurality of switches controlled based ona logic control signal so as to selectively isolate the first and secondstorage elements from the analog input signal, wherein the differentialseparating input stage includes a push-pull stage at the input of thedifferential separating input stage such that the push-pull stagereceives the analog input signal, the push-pull stage being connected tothe switches.
 12. The information handling system as defined in claim11, wherein the analog input signal is supplied to the emitters oftransistors that form the push-pull input stage, and the collectors ofthe transistors are connected to the switches.
 13. The informationhandling system as defined in claim 12, wherein the switches form ECLlogic gates configurations.
 14. The information handling system asdefined in claim 12, wherein the transistors that form the push-pullinput stage are part of current mirror circuits.
 15. The informationhandling system as defined in claim 11, wherein the control signalcontrols transistors for a ground portion of the input stage, and acomplement of the control signal controls transistors for a supplyvoltage portion of the input stage.
 16. The information handling systemas defined in claim 11, wherein the switches provide a low impedancepath during the hold operating phase.
 17. The information handlingsystem as defined in claim 11, wherein the differential separating inputstage has a quasi-differential architecture.